1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having low and high breakdown voltage transistors.
2. Description of the Prior Art
A semiconductor device comprising transistors employed for driving/controlling a motor or an air bag for a car, for example, is described as an exemplary conventional semiconductor device. In this type of semiconductor device, low and high breakdown voltage bipolar transistors and a CMOS (complementary metal oxide semiconductor) transistor are formed on the same semiconductor substrate.
The low and high breakdown voltage bipolar transistors are described with reference to the structure of the semiconductor device, and the low and high breakdown voltage bipolar transistors and the CMOS transistor are described with reference to a method of fabricating the semiconductor device.
FIG. 25 is a schematic sectional view showing the structure of a conventional semiconductor device. Referring to FIG. 25, both low and high breakdown voltage npn bipolar transistors are formed on regions of a p-type silicon substrate 109 electrically isolated from the remaining elements by p+ diffusion layers 110 and 111. Each of the low and high breakdown voltage npn bipolar transistors has a collector 108, a base 103a or 103b and an emitter 104.
In the low breakdown voltage npn bipolar transistor, the collector 108 has an n+ diffusion layer 105 formed on the p-type silicon substrate 109, an nxe2x88x92 epitaxial layer 106 formed on the p-type silicon substrate 109, and an nxe2x88x92 diffusion layer 107a and an n+ diffusion layer 107b formed on the surface of the nxe2x88x92 epitaxial layer 106. The base 103a has a p-type diffusion layer 130 formed on the surface of the nxe2x88x92 epitaxial layer 106 and a p+ diffusion layer 102b formed on the surface of the p-type diffusion layer 130. The emitter 104 has an nxe2x88x92 diffusion layer 104a and an n+ diffusion layer 104b formed on the surface of the p-type diffusion layer 130.
Field oxide films 112 are selectively formed to electrically isolate the base 103a, the emitter 104 and the collector 108 from each other. In a region of the low breakdown voltage npn bipolar transistor held between the p+ diffusion layer 102b and the emitter 104, however, no field oxide film 112 is formed on the surface of the p-type diffusion layer 130.
In the high breakdown voltage npn bipolar transistor, the base 103b has a p+ diffusion layer 102a formed on the surface of the nxe2x88x92 epitaxial layer 106 in a larger diffusion depth than the p-type diffusion layer 130, a p+ diffusion layer 102b formed on the surface of the p+ diffusion layer 102a and a p+ diffusion layer 101 enclosing the lower portions of the emitter 104 and the p+ diffusion layer 102b. 
Field oxide films 112 are formed on the p+ diffusion layers 101 and 102a held between the p+ diffusion layer 102b and the emitter 104.
The remaining structure of the high breakdown voltage npn bipolar transistor is substantially identical to that of the low breakdown voltage npn bipolar transistor, and hence components of the high breakdown voltage npn bipolar transistor identical to those of the low breakdown voltage npn bipolar transistor are denoted by the same reference numerals, not to repeat redundant description.
An interlayer isolation layer 113 is formed to cover the low and high breakdown voltage npn bipolar transistors, and electrodes 114 are formed to be electrically connected with the collectors 108, the bases 103a and 103b and the emitters 104 respectively.
A method of fabricating the conventional semiconductor device is now described.
FIGS. 26 to 30 are schematic sectional views successively showing steps in the method of fabricating the conventional semiconductor device. Referring to FIG. 26, the nxe2x88x92 epitaxial layer 106 is formed on the p-type silicon substrate 109 through the n+ diffusion layers 105 and the p+ diffusion layers 110.
Referring to FIG. 27, an nxe2x88x92 diffusion layer 122 is formed on a CMOS transistor region, followed by formation of the p+ diffusion layers 102a and the pxe2x88x92 diffusion layers 111 for element isolation.
Thereafter the field oxide films 112 are selectively formed on the surface of the substrate 109 by a general LOCOS (local oxidation of silicon) method. Thereafter boron ions are selectively implanted thereby forming the p+ diffusion layers 101 in the p+ diffusion layers 102a and 111.
Thin oxide films 121 are formed on portions of the surface of the substrate 109 formed with no field oxide films 112.
Referring to FIG. 28, gate electrodes consisting of films 123 of polycrystalline silicon (hereinafter referred to as doped polysilicon) doped with an impurity and tungsten silicide films 124 are formed on the CMOS transistor region. Thereafter the p-type diffusion layer 130 is formed on the low breakdown voltage npn bipolar transistor region. Further, the nxe2x88x92 diffusion layers 104a and 107a and nxe2x88x92 diffusion layers 125a are formed on the respective transistor regions.
Referring to FIG. 29, a silicon oxide film (not shown) is formed to cover the overall surface and the overall surface of this silicon oxide film is thereafter anisotropically etched for forming side wall insulating layers 126 covering the side surfaces of the gate electrodes 123 and 124. The thin silicon oxide films 121 are removed from the portions formed with no field oxide films 112 by the anisotropic etching for forming the side wall insulating layers 126, for partially exposing the surface of the substrate 109.
In this state, the n+ diffusion layers 104b and 107b and n+ diffusion layers 125b are formed on the respective transistor regions. In order to form these n+ diffusion layers 104b, 107b and 125b, arsenic is implanted into prescribed regions of the semiconductor substrate 109 and thereafter heat treatment is performed at a temperature of 900xc2x0 C. Thereafter the p+ diffusion layers 102b are formed on the low and high breakdown voltage npn bipolar transistor regions, and p+ diffusion layers 127 for defining source/drain regions are formed on the CMOS transistor region.
Referring to FIG. 30, the interlayer isolation layer 113 is formed to cover the overall surface, and thereafter the electrodes 114 are formed in contact with the respective diffusion layers.
In the aforementioned semiconductor device, the current amplification factor hFE characteristic of the low breakdown voltage npn bipolar transistor remarkably disperses in the wafer plane, and the fabrication steps are disadvantageously complicated. These problems are now described.
The inventors have evaluated collector current IC dependency of the current amplification factor hFE as to the conventional low breakdown voltage npn bipolar transistor. It has consequently been proved that the current amplification factor hFE remarkably disperses in the wafer plane. FIGS. 31B to 31F show the results.
FIGS. 31B to 31F are graphs showing the results evaluated on five measuring points 1 to 5 in the wafer plane shown in FIG. 31A respectively. It is understood from these graphs that the values of the current amplification factor hFE for a specific collector current IC vary and disperse in the wafer plane.
The current amplification factor hFE is defined as the ratio (IC/IB) of the collector current IC to a base current IB. In order to investigate the cause for such dispersion of the current amplification factor hFE, base-to-emitter voltage VEB dependency of the collector current IC and base-to-emitter voltage VEB dependency of the base current IB were evaluated respectively.
Referring to FIG. 32 showing partial results of the evaluation, results on the measuring points 3 and 5 exhibiting the largest changes among the five measuring points 1 to 5 in the wafer plane are plotted on the same graph. As shown in FIG. 32, the curves are substantially consistent with each other as to the base-to-emitter voltage VEB dependency of the collector current IC. Thus, it is conceivable that dispersion of the collector current IC in the wafer plane is extremely small.
Noting the curves showing the base-to-emitter voltage VEB dependency of the base current IB, however, it is understood that the curves at the measuring points 5 and 3 are inconsistent with each other. In other words, it is understood that the base current IB disperses in the wafer plane. Thus, it is conceivable that dispersion of the current amplification factor hFE results from such dispersion of the base current IB.
FIG. 33 illustrates respective components flowing in the low breakdown voltage npn bipolar transistor. Referring to FIG. 33, the current components in the bipolar transistor generally includes an electron injection component Idiff,B (component 1) into a base, a hole injection component Idiff,E (component 2) into an emitter, a recombination component Irec (component 3) in an emitter depletion layer, a recombination component xcex1T (component 4) in the base and a recombination component Isur (component 5) on the surface of the base.
The quantity of the base current IB corresponds to the total of the components 2, 3, 4 and 5 among these components. These components are approximately expressed as follows:                               I                      diff            ,            E                          ≈                              qD            pE                    ⁢                                    n              i              2                                                      N                DE                            ·                              W                E                                              ⁢                      exp            ⁡                          (                                                qV                  EB                                kT                            )                                                          (        1        )                                          I          rec                ≈                              1            2                    ⁢          q          ⁢                                                    n                i                                            τ                o                                      ·                          W              EB                        ·                          exp              ⁡                              (                                                      qV                    EB                                                        2                    ⁢                    kT                                                  )                                                                        (        2        )                                          α          T                ≈                  1          -                                    1              2                        ⁢                                          (                                                      W                    B                                                        L                    nB                                                  )                            2                                                          (        3        )                                          I          sur                ≈                              qS            n                    ⁢                                    n              i              2                                      N              AB                                ⁢                      exp            ⁡                          (                                                qV                  EB                                kT                            )                                ⁢                      A            s                                              (        4        )            
where DpE represents the hole diffusion constant in the emitter, NDE represents the impurity concentration in the emitter, NAB represents the impurity concentration in the base, Sn represents the surface recombination velocity of electrons, AS represents the effective recombination area, LnB represents the electron diffusion length in the base, WE represents the emitter width, WB represents the base width, WEB represents the width of the depletion layer between the emitter and the base, xcfx84o represents the effective life in a reverse bias depletion layer, k represents the Boltzmann""s constant, ni represents the electron density in an intrinsic semiconductor, T represents the absolute temperature, and q represents the charge quantity of electrons.
The recombination component (component 4) in the base, reducing by recombination while minority carriers pass through the base, quantitatively expresses the ratio of minority carriers reaching the base and a collector depletion layer among those injected into the base, and can be expressed in the carry-over factor xcex1T.
From the above expressions (1) to (4), it is understood that the impurity concentration NDE in the emitter and the impurity concentration NAB in the base concern with causes for the dispersion of the base current IB.
In the conventional fabrication method, the heat treatment is performed in a nitrogen atmosphere in the step shown in FIG. 29 while exposing the surface of the p-type diffusion layer 130 defining the base of the low breakdown voltage npn bipolar transistor. At this time, boron evaporates (diffuses out) from the surface of the p-type diffusion layer 130. Thus, it is conceivable that the conventional semiconductor device has a structure readily allowing evaporation of boron in the fabrication steps with different quantities in the wafer plane and hence the base current IB disperses in the wafer plane to result in remarkable dispersion of the current amplification factor hFE in the wafer plane.
In the conventional semiconductor device, the diffusion depths of the p-type diffusion layer 130 and the p+ diffusion layer 102a are different from each other, as shown in FIG. 25. Therefore, the p-type diffusion layer 130 and the p+ diffusion layer 102a must be formed in different steps (FIGS. 27 and 28), leading to complicated fabrication steps.
An object of the present invention is to suppress dispersion of a current amplification factor hFE characteristic in a wafer plane.
Another object of the present invention is to fabricate a low breakdown voltage transistor and a high breakdown voltage transistor through simple steps.
A semiconductor device according to the present invention has low and high breakdown voltage transistors formed on a major surface of a semiconductor substrate, and the low breakdown voltage transistor includes a field insulating layer, a base first impurity region of a first conductive type, a emitter first impurity region of a second conductive type and a base second impurity region of a first conductivity type. The field insulating layer is formed on the major surface of the semiconductor substrate. The base first impurity region is formed in a first side of the major surface in first and second sides of the major surface holding at least a part of the field insulating layer therebetween. The emitter first impurity region is formed in the second side of the major surface in the first and second sides of the major surface holding at least the part of the field insulating layer therebetween. The base second impurity region is located between the base first impurity region and the emitter first impurity region and immediately under the field insulating layer.
In the semiconductor device according to the present invention, the field insulating layer is located immediately on the base second impurity region located between the base first impurity region and the emitter first impurity region. Therefore, an impurity such as boron is prevented from evaporating from this portion. Thus, the quantity of an evaporating impurity can be reduced for suppressing increase of dispersion of the current amplification factor hFE in a wafer plane.
In the aforementioned semiconductor device, the low breakdown voltage transistor preferably withstands a voltage of less than 30 V, and the high breakdown voltage transistor preferably withstands a voltage of at least 30 V.
Thus, increase of dispersion of the current amplification factor hFE in the wafer plane can be suppressed in the low breakdown voltage transistor withstanding a voltage of less than 30 V.
In the aforementioned semiconductor device, the low breakdown voltage transistor preferably further includes a base third impurity region of a first conductivity type. The base second impurity region is formed in the major surface to enclose the base first impurity region and the emitter first impurity region, and has a lower impurity concentration than the base first impurity region. The base third impurity region encloses the emitter first impurity region in the major surface in the base second impurity region, has an opening in at least a partial region located immediately under the emitter first impurity region, and has a higher impurity concentration than the base second impurity region.
The base third impurity region thus encloses the emitter first impurity region on the major surface, whereby it is possible to prevent reduction of the emitter-to-collector breakdown voltage resulting from reduction of the surface concentration of the base second impurity region. In other words, reduction of the breakdown voltage can be prevented by providing the base third impurity region having a higher impurity concentration than the base second impurity region and increasing the surface concentration of the base second impurity region.
Further, the field insulating layer can inhibit evaporation of a p-type impurity such as boron in the base second impurity region located on the major surface between the base first impurity region and the emitter first impurity region.
In the aforementioned semiconductor device, the high breakdown voltage transistor preferably includes a base fourth impurity region of a first conductivity type, a emitter second impurity region of a second conductivity type, a base fifth impurity region of a first conductivity type and a base sixth impurity region of a first conductivity type. The base fourth impurity region is formed in the major surface of the semiconductor substrate. The emitter second impurity region is formed in the major surface at a space from the base fourth impurity region. The base fifth impurity region is formed in the major surface to enclose the base fourth impurity region and the emitter second impurity region and to be substantially identical in diffusion depth to the base second impurity region, and has a lower impurity concentration than the base fourth impurity region. The base sixth impurity region encloses the periphery of the emitter second impurity region, and has a higher impurity concentration than the base fifth impurity region.
Thus, the base fifth impurity region and the base second impurity region can be formed in the same step by setting the base fifth impurity region of the high breakdown voltage transistor at a diffusion depth substantially identical to that of the base second impurity region of the low breakdown voltage transistor. Therefore, the fabrication steps can be simplified.
In the aforementioned semiconductor device, the low breakdown voltage transistor preferably further includes a second conductivity type collector impurity region. The base second impurity region encloses the overall portion of the emitter first impurity region located under the major surface, and is electrically connected to the base first impurity region. The collector impurity region is in contact with the base second impurity region. The junction between the base second impurity region and the collector impurity region has an irregular part reflecting an irregular shape formed by the first side of the major surface, the second side of the major surface and the upper surface of at least the part of the field insulating layer.
Thus, the field insulating layer can suppress evaporation of a p-type impurity such as boron in the base second impurity region located on the major surface between the base first impurity region and the emitter first impurity region.
In the aforementioned semiconductor device, the high breakdown voltage transistor preferably includes a base third impurity region of a first conductivity type, a emitter second impurity region of a second conductivity type, a base fourth impurity region of a first conductivity type and a base fifth impurity region of a first conductivity type. The base third impurity region is formed in the major surface of the semiconductor substrate. The emitter second impurity region is formed in the major surface at a space from the base third impurity region. The base fourth impurity region is formed in the major surface of the semiconductor substrate to enclose the base third impurity region and the emitter second impurity region, and has a lower impurity concentration than the base third impurity region. The base fifth impurity region encloses the periphery of the emitter second impurity region, and has a higher impurity concentration than the base fourth impurity region.
Thus, the low breakdown voltage transistor has no layer corresponding to the base fourth impurity region of the high breakdown voltage transistor, and hence the base fourth impurity region and a region of the low breakdown voltage transistor corresponding thereto may not be formed in different steps. Therefore, the fabrication steps can be simplified.
A method of fabricating a semiconductor device according to the present invention is a method of fabricating a semiconductor device having low and high breakdown voltage transistors formed on a major surface of a semiconductor substrate, and a step of forming the low breakdown voltage transistor includes the following steps:
First, a field insulating layer is selectively formed on the major surface. A base first impurity region of a first conductivity type is formed in a first side of the major surface in first and second sides of the major surface holding at least a part of the field insulating layer therebetween, and a emitter first impurity region of a second conductivity type is formed in the second side of the major surface. A base second impurity region of a first conductivity type located at least immediately under the field insulating layer is formed either before or after formation of the field insulating layer.
In the method of fabricating a semiconductor device according to the present invention, the field insulating layer is located immediately on the base second impurity region held between the base first impurity region and the emitter first impurity region. Therefore, an impurity such as boron is prevented from evaporating from this portion. Thus, the quantity of an evaporating impurity can be reduced for suppressing increase of dispersion of the current amplification factor hFE in the wafer plane.
In the aforementioned method of fabricating a semiconductor device, the low breakdown voltage transistor preferably withstands a voltage of less than 30 V, and the high breakdown voltage transistor preferably withstands a voltage of at least 30 V.
Thus, increase of dispersion of the current amplification factor hFE in the wafer plane can be suppressed in the low breakdown voltage transistor withstanding a voltage of less than 30 V.
In the aforementioned method of fabricating a semiconductor device, the base second impurity region is preferably formed on the major surface before forming the field insulating layer. The base first impurity region, the emitter first impurity region and at least the part of the field insulating layer are formed on the major surface in the base second impurity region.
Thus, the field insulating layer can suppress evaporation of a p-type impurity such as boron in the base second impurity region located on the major surface between the base first impurity region and the emitter first impurity region.
In the aforementioned method of fabricating a semiconductor device, the step of forming the low breakdown voltage transistor preferably further includes a step of forming a base third impurity region of a first conductivity type having a higher impurity concentration than the base second impurity region to enclose a region formed with the emitter first impurity region on the major surface in the base second impurity region and to have an opening at least in a partial region located immediately under the emitter first impurity region after formation of the field insulating layer.
Thus, the base third impurity region encloses the emitter first impurity region on the major surface, whereby it is possible to prevent reduction of the emitter-to-collector breakdown voltage resulting from reduction of the surface concentration of the base second impurity region. In other words, reduction of the breakdown voltage can be prevented by providing the base third impurity region having a higher impurity concentration than the base second impurity region and increasing the surface concentration of the base second impurity region.
In the aforementioned method of fabricating a semiconductor device, a step of forming the high breakdown voltage transistor preferably includes steps of forming a base fourth impurity region of a first conductivity type in the major surface in the same step as that for the base first impurity region, forming a emitter second impurity region of a second conductivity type in the major surface at a space from the base fourth impurity region in the same step as that for the emitter first impurity region, forming a base fifth impurity region of a first conductivity type in the major surface to enclose the base fourth impurity region and the emitter second impurity region in the same step as that for the base second impurity region, and forming a base sixth impurity region of a first conductivity type to enclose the emitter second impurity region in the same step as that for the base third impurity region.
Thus, the base fifth impurity region of the high breakdown voltage transistor is formed in the same step as that for the base second impurity region of the low breakdown voltage transistor, whereby the fabrication steps can be simplified.
In the aforementioned method of fabricating a semiconductor device, the step of forming the low breakdown voltage transistor preferably further includes a step of forming a collector impurity region of a second conductivity type before formation of the field insulating layer. The base second impurity region is formed to enclose the emitter first impurity region so that the junction between the base second impurity region and the collector impurity region has an irregular part reflecting an irregular shape formed by the first side of the major surface, the second side of the major surface and the upper surface of at least the part of the field insulating layer after formation of the field insulating layer.
Thus, the field insulating layer can suppress evaporation of a p-type impurity such as boron in the base second impurity region located on the major surface between the base first impurity region and the emitter first impurity region.
In the aforementioned method of fabricating a semiconductor device, a step of forming the high breakdown voltage transistor preferably includes steps of forming a base third impurity region of a first conductivity type in the major surface in the same step as that for the base first impurity region, forming a emitter second impurity region of a second conductivity type in the major surface at a space from the base third impurity region in the same step as that for the emitter first impurity region, forming a base fourth impurity region of a first conductivity type in the major surface to enclose the base third impurity region and the emitter second impurity region after formation of the collector impurity region and before formation of the field insulating layer and forming a base fifth impurity region of a first conductivity type to enclose the emitter second impurity region and to have a higher impurity concentration than the base fourth impurity region in the same step as that for the base second impurity region.
Thus, the low breakdown voltage transistor has no layer corresponding to the base fourth impurity region of the high breakdown voltage transistor, whereby the base fourth impurity region and a region of the low breakdown voltage transistor corresponding thereto may not be formed in different steps. Therefore, the fabrication steps can be simplified.
Throughout the specification, the term xe2x80x9cfield insulating layerxe2x80x9d indicates an insulating layer such as a field oxide film formed by a method equivalent to the LOCOS method.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.